1. Field of the Invention
The present invention relates to a discrete cosine transform circuit which can be used in compression/extension processing of digital voice data in a digital voice recording and reproduction devices.
2. Description of the Related Art
FIG. 1 is a block diagram showing a processing device which performs encoding/decoding of digitized voice data. At the time of recording, the entered voice signal is first converted to digital voice data by A/D (analog to digital) converter 2. The digital voice data is divided to three, low, medium, and high, frequency bandwidths using QMF (quadrature mirror filter) circuit 4. The digital time series voice data is converted to frequency component data using DCT (discrete cosine transform) circuit 6, and further quantized by a quantizing unit 8. The generated or encoded data is supplied to the next-stage processing circuit, and recorded in a predetermined recording medium.
At the time of reproduction, processing reverse to the processing described above is performed. Specifically, an inverse quantizing unit 10, IDCT (inverse discrete cosine transform) circuit 12, IQMF (inverse quadrature mirror filter) circuit 14 and D/A (digital to analog) converter 16 perform the conversion reverse to the conversion performed by the quantizing unit 8, DCT circuit 6, QMF circuit 4 and A/D converter 2. Specifically, a voice signal is reproduced from the recorded encoded data.
Additionally, DCT is useful for encoding/decoding voice signals, and is widely used. There are various types of DCT. For example, there is one type of DCT foruse in a voice recording/reproducing device which is represented by the following relational equation of 2M items of time series voice data y(n) represented by a time index n which is a continuous integer and M items of frequency component data X(k) represented by a wave number index k which is a continuous integer: ##EQU1##
The DCT is slightly modified from a basic DCT and is therefor termed a Modified DCT, and will hereinafter be abbreviated as MDCT. Moreover, the inverse modified DCT is hereinafter abbreviated as IMDCT.
As an algorithm for processing DCT at a high rate, a method is known in which FFT (fast Fourier transform) is used. By the algorithm using FFT, sequence y(n) is obtained from sequence X(k) in the MDCT. Conversely, sequence X(k) is obtained from sequence y(n) in IMDCT.
More specifically, the relational equation (1) of the time series voice data y(n) and the frequency component data X(k) is represented in a format suitable for the calculation of IMDCT. For MDCT, calculation is performed based on equation (6) below.
The calculation algorithm regarding IMDCT based on the equation (1) will be described hereinafter. First, the data before conversion, i.e., sequence X(k) is re-arranged and re-constructed according to the predetermined rule to define a new sequence U(k). Based on U(k), Z(j) represented in the following equation is defined. Additionally, in the equation, i denotes an imaginary number unit, and .psi.(j) denotes the predetermined function of j. EQU z(j)=(U(2j)+iU(2j+1).multidot.exp(i.psi.(j)) (2)
Furthermore, z(n) defined by the following equation is obtained from z(j). ##EQU2##
In order to calculate the equation (3) at high speed, FFT is used. As is well known, FFT calculates the above equation (3) by repeating the arithmetic operation represented by the following equation. Additionally, .psi.'(j) is the predetermined function of j. EQU z(j.sub.1)+Z(j.sub.2).multidot.exp(i.psi.'(j)) (4)
In IMDCT, u(n) defined in the following equation (5) is obtained from the z(n), and the sequence u(n) is re-arranged and re-constructed to obtain the time series voice data y(n). Additionally, a.sub.0 to a.sub.3 are proportional coefficients defined for every n. EQU u(n)=a.sub.0.multidot.Rez(n)+a.sub.1.multidot.Rez(M/2-1-n)+a.sub. 2.multidot.Imz(n)+a.sub.3.multidot.Imz(M/2-1-n) EQU u(M-1-n)=a.sub.2.multidot.Rez(n)-a.sub.3.multidot.Rez(M/2-1-n)-a. sub.0.multidot.Imz(n)+a.sub.1.multidot.Imz(M/2-1-n) (5)
On the other hand, for MDCT, the following relational equation is used to obtain the frequency component data X(K) from the sequence x(n) based on the time series voice data y(n). ##EQU3##
The equations (1) and (6) have substantially the same format except the coefficient 2/M. Therefore, the calculation algorithm of MDCT is expected to be similar to that of the IMDCT described above. In practice, the calculation algorithm of MDCT based on the equation (6) is as follows, and has points common with the IMDCT algorithm, though some points differ.
First, a new sequence x'(n) is defined by the sum (or difference) of the predetermined elements of the data before conversion, i.e., the sequence x(n) as shown in the following equation:
x'(n)=x(n.sub.1)+x(n.sub.2) or x(n.sub.1)-x(n.sub.2) (7)
This process is not included in IMDCT. Based on the x'(n), z(j) is defined in the following equation having the same format as that of the equation (2): EQU z(j)=(x'(2j)+ix'(2j+1)).multidot.exp(i.psi.(j)) (8)
Furthermore, Z(k) is obtained from the z(j) as defined in the following equation:
##EQU4##
The equation (9) has the same format as that of the equation (3), FFT is also used in the high speed calculation in the same manner as in the equation (3), and the arithmetic operation is performed in the following format: EQU z(j.sub.1)+z(j.sub.2).multidot.exp(i.psi.'(j)) (10)
In MDCT, the frequency component data X(k) is obtained from the Z(k) by the following equation (11):
X(k)=b.sub.0.multidot.ReZ(k)+b.sub.1.multidot.ReZ(M/2-1-k)+b.sub. 2.multidot.ImZ(k)+b.sub.3.multidot.ImZ(M/2-1-k) EQU X(M-1-k)=b.sub.2.multidot.ReZ(k)-b.sub.3.multidot.ReZ(M/2-1-k)-b. sub.0.multidot.ImZ(k)+b.sub.1.multidot.ImZ(M/2-1-k) (11)
In the equation, b.sub.0 to b.sub.3 are proportional coefficients determined for each k. When the proportional coefficient a.sub.L (L=0 to 3) determined for each n is represented as a.sub.L =a.sub.L (n) or the proportional coefficient b.sub.L (L=0 to 3) is represented as b.sub.L =b.sub.L (k), the following relationship is established between the coefficients: EQU b.sub.L (j)=a.sub.L (j)x2/M (12)
FIG. 2 is a block diagram showing a conventional IMDCT circuit in which the aforementioned IMDCT arithmetic operation is realized. The data before conversion, i.e., the frequency component data X(k), is stored in RAM (random access memory) 20. The RAM 20 is also constituted to store the results during the course of the arithmetic operation. For example, the proportional coefficient a.sub.L (L=0 to 3) is stored in ROM (read only memory) 22. The value read from RAM 20 and held in a register 26 and the value read from ROM 22 and held in a register 28 are transmitted to a multiplier 24, which multiplies these values to transmit them to either register 30 or 32.
An adder/subtracter 34 has two inputs A, B, which are connected to selectors 36, 38. The registers 26 and 30 are connected to the input side of the selector 36. Therefore, the selector 36 can selectively supply the data stored in RAM 20 or the data multiplied by the multiplier 24 to one input terminal A of the adder/subtracter 34. On the other hand, registers 42, 44 are connected to the selector 38 via a selector 40, while the register 32 is connected to the input side of the selector 38. Therefore, the selector 38 can selectively supply the value stored in the register 32 (e.g., the value obtained by multiplying the data stored in RAM 20 by the multiplier 24) or the output result of the adder/subtracter 34 to the other input terminal B of the adder/subtracter 34. The output of the adder/subtracter 34 can be returned and written to RAM 20 via the register 42.
In the conversion of the time series voice data y(n) and the frequency component data X(k), for the time series voice data y(n), consecutive 2M items of data are regarded as one block, and the data is handled block by block. One generated block of time series voice data is stored in RAM 44. In order to minimize the distortion of voice at boundaries of the blocks, the range of the block is determined in such a manner that the end of the preceding block and the top of the following block are overlapped with each other. In the overlapped area, the data values of these blocks are added to generate the final voice data y(n). To overlap the data, the voice data stored in RAM 44 can be returned to the adder/subtracter 34. Specifically, the value read from RAM 44 is transmitted to a selector 46 placed between the multiplier 24 and the register 32. The selector 46 selects the output of the multiplier 24 or the output of RAM 44 to transmit the selected value to the adder/subtracter 34 via the selector 38.
The aforementioned arithmetic operation in the conventional circuit will next be described. First, by developing the right side of the equation (2), Z(j) is represented in the following equation: EQU Z(j)=(U(2j).multidot.cos .psi.(j)-U(2j+1).multidot.sin .psi.(j))+i(U(2j+1).multidot.cos .psi.(j)-U(2j).multidot.sin .psi.(j)) (13)
Therefore, when the data U(k) is stored in RAM 20, and sin .psi.(j), cos .psi.(j) are stored in ROM 22, the real-number and imaginary-number portions of Z(j) are calculated by successively using the multiplier 24 and the adder/subtracter 34. The operation results of the real-number and imaginary-number portions outputted from the adder/subtracter 34 are stored in RAM 20.
As described above, z (n) is obtained by repeating the arithmetic operation shown in the equation (4). When Z(j) stored in RAM 20 is transmitted to the adder/subtracter 34 via the register 26 and the selector 36 without passing through the multiplier 24, the first term on the right side of the equation (4) is supplied to one terminal A of the adder/subtracter 34. Moreover, the second term on the right side is generated by reading Z(j) stored in RAM 20 and exp(i.psi.'(j)) stored in ROM 22 and multiplying them in the multiplier 24. The multiplied value is supplied to the other terminal B of the adder/subtracter 34 via the selector 46, the register 32 and the selector 38. The adder/subtracter 34 adds the first and second terms of the equation (4), and the result is stored in RAM 20. The calculation of z(n) is also a complex arithmetic operation, and the real-number portion and the imaginary-number portion are separately calculated in the circuit.
By the arithmetic operation described above, Rez(n), Rez(M/2-1-n), Imz(n), Imz(M/2-1-n) for use in the arithmetic operation of the equation (5) are stored in RAM 20. Moreover, the proportional coefficient aL (L=0 to 3) is stored in ROM 22. The calculation of the equation (5) is performed by sequentially calculating the terms from the first term on the right side by the multiplier 24 and cumulatively adding/subtracting the values by the adder/subtracter 34.
The calculation will be described in more detail. For example, Rez(n) is read from RAM 20 and stored in the register 26. On the other hand, a.sub.0 is read from ROM 22 and stored in the register 28. These values are multiplied in the multiplier 24 and stored in the register 32. Subsequently, Rez(M/2-1-n) is read from RAM 20 and stored in the register 26, while a.sub.1 is read from ROM 22 and stored in the register 28. It is herein noted that the content of the register 26 is overwritten and changed from Rez(n) stored for the calculation of the first term to Rez(M/2-1-n) for use in the calculation of the second term. The Rez(M/2-1-n) and a, are multiplied in the multiplier 24 and stored in the register 30. The adder/subtracter 34 calculates "A+B" in accordance with the contents of the registers 32 and 30 and transmits the result to the register 44.
Subsequently, the third term is calculated in the same manner as the first and second terms, and stored in the register 30. The adder/subtracter 34 calculates "A+B" in accordance with the content of the register 30 and the cumulative added value up to the second term supplied from the register 44, and transmits an output to the register 44. The fourth term is calculated in the same manner, and added to the added value up to the third term, then the result is returned to RAM 20. Thereafter, the second equation of the equation (5) is calculated in the same manner as the first equation. In the calculation of the second equation, the second term transmitted to the input terminal A corresponds to the subtraction from the first term supplied to the input terminal B, and the adder/subtracter 34 performs "B-A".
As described above, there are many common aspects between arithmetic operations for IMDCT and MDCT. For example, relational equations (8), (9), (11) for MDCT have the same format as relational equations (2), (3), (5) for INDT. However, the MDCT arithmetic operation initially includes a process for relational equation (7). Also, although relational equations (5) and (11) have the same format, they use different coefficients, i.e., a.sub.L and b.sub.L (L=0.about.3). These are the differences between the arithmetic operations for IMDCT and MDCT.
Therefore, it is impossible for a conventional IMDCT circuit to perform the above arithmetic operation for MDCT when data before MDCT conversion is simply stored in the RAM 20 and the RAM 44 thereof. For example, although relational equation (7) means that addition/subtraction is carried out using operand data intact, i.e., without multiplication, in a conventional IMDCT circuit, non-multiplied data can be supplied to the adder/subtracter 34 only via one of the inputs thereof from the RAM 20 and 44. Therefore, the conventional IMDCT circuit cannot calculate relational equation (7), and thus the arithmetic operation for MDCT. In order to solve this problem, the adder/subtracter 34 must have a structure capable of receiving non-multiplied data via both inputs thereof at one time. Such a circuit inevitably has a complicated structure when constructed by using only the related art.
Moreover, it may be possible to calculate relational equation (11) when a proportional coefficient b.sub.L (L=0.about.3) is stored in the ROM 22 as well as proportional coefficient a.sub.L. However, in that case, proportional coefficients must be read from different addresses in the ROM 22 when calculating relational equations (5) and (11). This results in complicating the structure of an address generation circuit.
In view of the above, conventionally, there is a problem that the entire circuit has a large circuitry size because IMDCT and MDCT circuits are structured as separate circuits. When they are structured as a single circuit, the resultant circuit has a complicated structure.